DATE
July 7 – 10, 2025
SCHEDULE
2:00 pm – 7:00 pm (CET Madrid)
Online training course
20 hours
4 days × 5h
It will not leave you indifferent
This course focuses on the methodology for the development and verification of programmable logic in FPGAs and SoCs using VHDL, following the safety standards required in mission-critical projects.
Its objective is to present the methodologies, tools, and best design practices to successfully tackle FPGA verification.
Includes practical exercises on VHDL code verification using the ModelSim tool, where the certification evidence required by the safety standards will be generated.
The course is aimed at people with notions in the development of projects under safety regulations from the software field. Basic knowledge of VHDL is required.
Attendees will receive the course slides in pdf format and the different solved practical cases.
The Trainer
Electronics and Telecommunications Engineer and Master in Robotics, with twenty years of experience in embedded systems. Combines experience in hardware and software development with the certification of critical systems.
Agenda
• Planning
• Requirements Capture
• Detailed Design
• Requirements Capture
• Detailed Design
• Implementation
• Verification & Validation
• RTL versus behavioral code
• Good coding practices & coding standards
• Numeric libraries
• SEU Mitigation
• Fault-tolerant systems
• Secure your desing
• Basics of regression testing
• HDL Simulation
• Cross-clock domain analysis
• Static timing analysis
• Netlist simulation
• Hardware testing
• Functional coverage
• Assertions
• Constrained random verification
• UVVM
• VUnit
• Design tools and verification tools
• Tool qualification versus tool assessment
• Creation of a demo project
• Python for VHDL testing
• Installing 3rd party libraries
• Libraries for data analysis
• Regression testing
• Generating test data
• Synthesis and implementation
• Back annotated testing
